Memory ICs comprise a plurality of memory cells interconnected by bitlines and wordlines. A memory cell includes a transistor coupled to a capacitor for storage of a bit of information. To realize high density memory ICs, the memory cells employ a capacitor over plug structure (COP), as shown in FIG. 1. The structure includes a capacitor 140 having a dielectric layer 146 located between first and second electrodes 141 and 142. The capacitor is coupled to a conductive plug 170.
Typically, a high temperature anneal in an oxygen (O2) ambient is required to improve the properties of the dielectric layer, particularly for high K dielectric and ferroelectric materials. During the anneal, O2 diffuses through the capacitor and oxidizes the plug. This can lead to performance degradation and, in some cases, failure as a result of increased plug resisitivity or electrical open connections.
To prevent diffusion of oxygen through the capacitor, a barrier layer 148 formed from iridium is provided between the lower electrode and the plug. An adhesion layer 149 is provided to promote adhesion between the barrier layer and interlevel dielectric layer 118, such as silicon dioxide (SiO2) or silicon nitride (SiN). Iridium is used due to its good barrier properties against O2. In conventional processing, the barrier layer and electrode have vertical grain boundaries 121 and 123 which connect at the interface 143, as shown in caption A. The connection of the vertical grain boundaries of the layers provides diffusion paths for O2. At high temperatures (e.g., >600° C.), O2 can easily diffuse through the grain boundaries of the barrier layer to oxidize the adhesion layer and the plug.
Also, in some applications, the upper surface of the plug 170 is above the upper surface of the dielectric layer 118, creating a step 271, as shown in FIG. 2. For example, the step is created due to the formation of a silicide layer 272 above the plug when polysilicon is used to form plug. The step has been found to undesirably degrade the structural properties of the barrier layer near the corner of the step, allowing oxygen to diffuse through the barrier layer and oxidizing the plug.
FIG. 3 shows a TEM of a conventional barrier layer 348 formed over a plug 370 with a step 371 of about 30 nm in height after being subjected to an anneal of about 650° C. in an O2 ambient for about 2 hours. An adhesion layer 349 comprising titanium is located beneath the barrier layer. As can be seen from the Figure, a top portion 372 of the plug is oxidized. The oxidization expands the plug, creating a bulge 388 which degrades the contact between the barrier layer and the plug. This results in high contact resistance, which can lead to performance degradation and/or failures.
From the foregoing discussion, it is desirable to provide an improved barrier layer for reducing oxidation of the plug in a capacitor over plug structure.